Selective spacer formation on transistors of different classes on the same device

ABSTRACT

A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

FIELD OF INVENTION

Semiconductor manufacturing.

BACKGROUND OF INVENTION

Metal-oxide-semiconductor (MOS) transistors are the primary building blocks for modem integrated circuits. A typical highly integrated circuit, such as a microelectronic device, can contain millions of transistors on a single silicon substrate no bigger than a thumbnail. Generally, a transistor, or device and hereinafter referred to interchangeably, includes a gate structure formed on a substrate with a source region and a drain region, separated from each other by the gate structure and formed within the substrate, adjacent to the gate structure. A transistor may be thought of as an electronic switch having three nodes. When a voltage is applied to a first node of the transistor, i.e., the gate, the flow of electric current between the other two nodes, i.e., the source and the drain regions, via a channel region below the gate, is modulated. For example, to turn one type of n-channel (NMOS) transistor “ON,” a positive voltage is applied to the gate, allowing electric current to flow between the source and drain. To turn this transistor “OFF,” zero volts is applied to the gate which cuts off the flow of electric current between the source and drain.

The type of transistor on a microelectronic device varies depending on its intended function. Examples of transistors include NMOS and PMOS transistors used in Logic circuits and NMOS and PMOS transistors used in SRAM circuits. Generally, the function of Memory transistors require less power (and therefore slower current flow) while Logic transistors require more power (and therefore faster current flow). Power (represented by the formula Power equals I×V, wherein I equals current and V equals voltage) is measured by the speed of electrons moving from the source and drain regions via the channel region. One method of controlling this movement, and hence the power of a given transistor, is to control the distance from the source region to the drain region. Typically, because Memory transistors require less power, the distance from the source region to the drain region is larger when compared to that of a Logic transistor.

Distance between the source region and the drain region also affects leakage of current flow in the OFF state. “Leakage” is the amount of current flowing through the transistor when in the OFF state. Although a given transistor is in the OFF state, a small amount of current continues to flow through the channel region. The total current of a transistor is measured by the current flow in both the ON and OFF states. That is, current (I) equals I_(ON)+I_(OFF), where I_(OFF) is very small compared to I_(ON). The greater the distance between the source region and the drain region, the smaller the leakage. However, the trade-off is that the overall speed of the transistor is lessened.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A illustrates an embodiment of a microelectronic device device.

FIG. 2A shows a cross-sectional side view of a portion of microelectronic device including an embodiment of a first class of transistor and an embodiment of a second class of transistor thereon.

FIG. 1B shows a cross-sectional side view of a MOS transistor.

FIG. 1C shows a cross-sectional side view of a SRAM transistor.

FIG. 2B shows FIG. 2A following the formation of a first deposition layer thereon.

FIG. 2C shows FIG. 2B following the formation of a blocking layer thereon.

FIG. 2D shows FIG. 2C following selective etching.

FIG. 2E shows FIG. 2D following the formation of a second deposition layer thereon.

FIG. 2F shows FIG. 2E following a selective etching process.

FIG. 2G shows FIG. 2F during a selective etching process.

FIG. 2H shows FIG. 2G following a selective etching process.

FIG. 2I shows FIG. 2G following an etching process.

FIG. 3 illustrates a schematic of an embodiment of one method of selectively depositing a spacer on a microelectronic device device.

FIG. 4 illustrates a schematic of an alternative embodiment of one method of selectively depositing a spacer on a microelectronic device.

FIG. 5 shows a computer system including microprocessor enclosed by a package mounted to a printed circuit board

DETAILED DESCRIPTION

Fabrication of transistors can involve the formation of “spacer” structures adjacent to gate structures. Spacers insulate gate stacks and provide distance between a source region and a drain region to, for example, decrease OFF state leakage, which consequentially reduces power. In some fabrication methods, a conformal layer is deposited on the substrate with a multitude of gate structures thereon. The conformal layer is then anisotropically etched leaving spacer structures adjacent to the gate structure. “Anisotropic etching” is an etch process that exhibits little or no undercutting, resulting in features whose sides are perpendicular to the underlying layer.

In some microelectronic device fabrication methods, efficiency of a device is increased by doping the source and drain regions with, for example, silicon-germanium SiGe or silicon-carbon SiC. SiGe can be introduced such that it can cause compressive strain on a channel region, which in turn increases the speed of holes traveling from the source region to the drain region of a PMOS device. SiC can be introduced such that it can cause tensile strain on a channel region, which in turn increases the speed of electrons traveling from the source region to the drain region of an NMOS device In some applications, however, conventional spacer structure fabrication methods do not allow for sufficient space between gate structures for doping of the source and drain regions alternating between gate to gate.

Current complementary metal-oxide-semiconductor (CMOS) fabrication processes for microelectronic devices incorporate both PMOS and NMOS multileg (isolated and somewhat randomly oriented) layout transistor devices and SRAM array devices on the same substrate. Due to the large number of SRAM devices in an array layout, the gate-to-gate space between SRAM devices is generally smaller compared to the gate-to-gate space between Logic transistors, which are fewer in number and randomly situated. In some applications, a first class of transistors situated on the same substrate as a second class of transistors can have a decrease in OFF state leakage at the expense of decreased power. In some embodiments, a first class of transistors can include transistors with a first predetermined sized spacer and a second class of transistors can include transistors with a second different predetermined sized spacer. Such an embodiment can be useful in, for example, a laptop computer battery in which speed of the computer may be compromised in return for a longer battery lifetime. In some embodiments, a method to accomplish this is to increase the size of the spacer. However, fabrication methods can involve depositing a conformal layer on a die with different classes of transistors situated thereon, which deposition does not discriminate between the different classes of transistors. As a result, the spacers formed thereafter are substantially the same thickness with respect to the different classes of transistors. Thus, while accomplishing reduction of OFF state leakage in one class of transistors, e.g., PMOS Logic transistors, this can result in largely degraded performance on certain transistors in which there is a small gate-to-gate space, such as in a SRAM transistor array or stacked devices, leading to degraded performance and, eventually, function failure.

In some applications, a microelectronic device, representatively shown in FIG. 1A, can include both Logic transistors 102 and other types of transistors 104 on the same die 100. Other types of transistors can include, but are not limited to, SRAM Memory, hereinafter collectively referred to as “non-Logic transistors.” Logic transistors generally require more power relative to non-Logic transistors. Thus, the distance between the source and drain regions can be smaller in Logic transistors when compared to non-Logic transistors. As a consequence, the I_(OFF) can be higher in Logic transistors when compared to non-Logic transistors. In some applications, such as those applications requiring a slower efficiency yet a longer life, the Logic transistors can be configured to have a low I_(OFF).

FIG. 1B represents an embodiment of MOS transistor 108. MOS transistor includes a gate structure 110, source region 112 and drain region 114 formed on substrate 124. The gate structure 110 can include spacers 118 located adjacent thereto. In the ON state, i.e., when negative voltage is applied, holes flow from source region 112 to drain region 114 via channel region 116, representatively shown by arrow 120. In the OFF state, i.e., when no voltage is applied, a small of amount of current, or leakage, continues to flow from source region 112 to drain region 114 via channel region 116. Leakage is a direct function of the distance between source region 112 and drain region 114, representatively shown by arrow 122. That is, the smaller gate structure 110 provides a smaller distance between source and drain regions 110 and 112, respectively. Such configuration generally allows for relatively increased speed at the cost of high leakage.

FIG. 1C represents an embodiment of an SRAM transistor 130. SRAM transistor includes gate structure 126 a gate structure 128, source region 130 and drain region 132 formed on substrate 138. Similar to the embodiment in FIG. 1B, a channel region 134 and spacers 136 are also provided. The distance between source 130 and drain 132 is representatively shown by arrow 136. The larger gate structure 128 provides a greater distance between source region 130 and drain region 132. Such configuration generally allows for relatively slower speed with low leakage.

On a die, MOS Logic transistors can be situated at random, while non-Logic transistors can be situated in an array. In some embodiments, an array takes up a larger space relative to the randomly situated Logic transistors on a given die. Thus, the gate-to-gate space, i.e., the pitch, should be as small as possible for array of non-Logic transistors, such as an SRAM array. For Logic transistors, the pitch can be approximately 180 nanometers (nm). For SRAM transistors, the pitch can be approximately 160 nm.

FIGS. 2A-2H illustrate an embodiment of a method for selectively forming a spacer on a gate structure of a first class of transistor. FIG. 2A shows a portion of a microelectronic device 100, representatively shown as die 200, including a substrate 202 with an embodiment of a transistor 204 of a first class and an embodiment of a transistor 214 of a second class situated thereon. Transistor 204 can include an etch stop 206, a gate electrode 208 and a dielectric 210, collectively, a gate structure 212. Etch stop portion 206 can be, for example, silicon nitride (Si₃N₄), oxynitride (SiO_(y)N_(x)) and the like; gate electrode 208 can be, for example, a polycrystalline semiconductor, such as polycrystalline silicon (polysilicon), polysilicon germanium (poly-SiGe) or a metal having, for example, a work function appropriate for a p-type or n-type semiconductor; and dielectric 210 can be a non-conductive material, such as silicon dioxide, silicon nitride and the like. Transistor 214 can include an etch stop 216, a gate electrode 218 and a dielectric 220, collectively, a gate structure 232. The materials of gate structure 222 can be similar to those of gate structure 212. In some embodiments, transistor 204 can be an NMOS or PMOS within an SRAM or NMOS Logic transistor and transistor 214 can be a PMOS Logic transistor.

FIG. 2B shows an embodiment of the formation of first deposition layer 224 on microelectronic device 100 of FIG. 2A. In some embodiments, first deposition layer 224 can be a dielectric material. In some embodiments, first deposition layer 224 can be conformal. First deposition layer 224 can be in a range of approximately 50 Angstroms (Å) to 1500 Å. In some embodiments, first deposition layer 224 can be in a range from approximately 200 Å to 600 Å. First deposition layer 227 can be applied by processes known in the art. Examples of such processes include, but are not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), low pressure CVD, plasma-enhanced CVD or any other suitable process.

FIG. 2C shows an embodiment of the selective formation of a blocking layer 226 on microelectronic device 100 of FIG. 2B. In some embodiments, blocking layer 226 can be a photo-imaging material, such as a photoresist. Photoresists can be applied by a process known as photolithography, also known as photomasking. “Photolithography” is a process used to selectively create patterns on a substrate surface. “Patterning” is the basic operation that removes specific portions of the uppermost layer at a given fabrication step on the substrate surface. Photoresists can be either negative or positive. In both forms, photoresists are three-component materials including a matrix, a photoactive compound and a solvent. For positive photoresists, the matrix may be a low-molecular weight novolac resin, the photoactive component may be a diazonaphthaquinone compound and the solvent system may be a mixture of n-butyl acetate, xylene and cellosolve acetate. For negative photoresists, the matrix may be cyclized synthetic rubber resin, the photoactive component may be a bis-arylazide compound and the solvent system may be an aromatic solvent. In some embodiments, blocking layer 226 can be selectively deposited on, or applied to, transistor 204 of the first class. In some embodiments, blocking layer 226 can be applied to an array of transistors.

FIG. 2D shows an embodiment of FIG. 2C following selective removal of first deposition layer 224. In some embodiments, first deposition layer 224 can be dry etched from gate structure 222 while blocking layer 226 remains on gate structure 212. Dry etching can be performed by such processes including, but not limited to, reactive ion etching, sputter etching and vapor phase etching. Dry etching can result in isotropic etching. “Isotropic etching” is a process in which etching occurs in all directions causing undercutting. After the dry etching is performed on the exposed portion of first deposition layer 224, blocking layer 226 can be removed from gate structure 212 by a process known as “ashing.” “Ashing” is a method of stripping photoresist that utilizes high energy gas, usually an oxygen plasma or ozone, to burn off photoresist. The result is gate structure 222 with a first spacer layer 228 adjacent thereto and gate structure 212 covered with first deposition layer 224 substantially or completely intact.

FIG. 2E shows an embodiment of FIG. 2D following the formation of a second deposition layer thereon. In some embodiments, second deposition layer 230 can be a dielectric material, which, in some applications, can be a different material than that of first deposition layer 227. Examples of dielectric materials comprising second deposition layer include, but are not limited to, nitrides such as (Si₃N₄), (SiO_(y)N_(x)) and the like. In some embodiments, the second deposition layer 230 can be conformal. Second deposition layer 230 can be in a range of approximately 100 Å to 1000 Å. In some embodiments, second deposition layer 230 can be in a range from approximately 200 Å to 600 Å. Second deposition layer 230 can be applied by processes known in the art, including, but not limited to, PVD, ALD, CVD, low pressure CVD, plasma-enhanced CVD or any other suitable process.

FIG. 2F shows an embodiment of FIG. 2E following removal of second deposition layer 230. In some embodiments, second deposition layer 230 can be dry etched from gate structures 212 and 222 of both transistors 204 and 214. Dry etching can be performed by such processes which include, but are not limited to, reactive ion etching, sputter etching and vapor phase etching. Dry etching can result in isotropic etching. After the etching, a bi-layer spacer 236 including first spacer layer 228 and second spacer layer 232 remains adjacent to gate structure 222 of transistor 214. Gate structure 212 of transistor 204, on the other hand, includes remaining first deposition layer 224 with removable spacer layer 234 adjacent thereto.

FIG. 2G shows an embodiment of FIG. 2F during a selective etching process of remaining first deposition layer 224 from gate structure 212. In some embodiments, remaining first deposition layer 224 can be wet etched from gate structure 212. Wet etching can be performed by dipping, spraying or otherwise applying a chemical solution to the substrate. Wet etching can result in isotropic etching which will etch at the same rate in both vertical and horizontal direction. In some embodiments, after the wet etching process, remaining second deposition layer 230 will be removed from gate structure 212 automatically. That is, because the remaining first deposition layer 224 has been removed by the wet etching process, removable spacer 234 has nothing with which to adhere (both at the bottom and at the side) and will automatically be effaced.

FIG. 2H shows an embodiment of FIG. 2G following the selective etching process described with respect to FIG. 2G. Gate structure 222 of transistor 214 will include bi-layer spacer 236 adjacent thereto and gate structure 212 of transistor 204 will not include any spacer as a result of embodiments of the method described with respect to FIGS. 2A-2G. In some embodiments, the bi-layer spacer 236 can be in the range of approximately 5 nm to 10 nm. It should be appreciated that the method embodied in FIGS. 2A-2H may be repeated on the same die to form more spacers.

In some embodiments, subsequent to the method embodied in FIGS. 2A-2H, a conventional spacer deposition process may be performed on the substrate. Such process may include depositing a conformal first deposition layer, dry etching the first deposition layer, depositing a conformal second deposition layer and dry etching the second deposition layer, resulting in spacer formed adjacent to a multitude of transistors. Thus, in some embodiments, a die which was subjected to a selective spacer deposition process may be subjected to subsequent selective spacer deposition processes or conventional spacer deposition processes to form spacers of varying sizes on transistors of varying classes (see FIG. 2I). For example, in some embodiments, a combination of at least one selective spacer deposition process and at least one conventional spacer deposition process may result in a first class of transistors having a spacer of from approximately 10 nm to 50 nm and a second class of transistors having a spacer of from approximately 50 nm to 100 nm. In some embodiments, the first class of transistors may be Logic transistors and the second class of transistors may be non-Logic transistors.

FIG. 3 represents a schematic of an embodiment of a selective spacer deposition process. A die can be formed with both Logic transistors and non-Logic transistors (300). In some embodiments, Logic transistors are situated randomly and Memory transistors are arranged in an array. A first deposition layer can be conformally deposited on the die (310). Then, a blocking layer can be selectively deposited on at least one non-PMOS transistor (320). A dry etch process can be performed on the first deposition layer (330). Subsequently, the blocking layer can be removed by ashing or any other suitable method (340). Thereafter, a second deposition layer can be conformally deposited on the die (350). A dry etch process can be performed on the second deposition layer (360). Any remaining first deposition layer may then be removed by a wet etching process or any other suitable process (370). Subsequent selective or non-selective deposition processes may then be optionally performed on the die (380).

FIG. 4 represents an alternative schematic of an embodiment of a selective spacer deposition process. A die can be formed with both Logic transistors and non-Logic transistors (400). In some embodiments, the non-Logic transistors can be Memory (SRAM) and Logic transistors. In some embodiments, Logic transistors are situated randomly and Memory transistors are arranged in an array. A first deposition layer can be conformally deposited on the die (410). A dry etch process can be performed on the first deposition layer leaving spacers on both Logic transistors and non-Logic transistors (420). Then, a blocking layer can be selectively deposited on at least one non-Logic transistor (430). A dry etch process can be performed on any unblocked spacer (440). In this manner, the size of any exposed unblocked spacer can be selectively partially or completely removed. Subsequently, the blocking layer can be removed by ashing or any other suitable method (450). Subsequent selective or non-selective deposition processes may then be optionally performed on the die (460).

According to embodiments of the above-described methods, a thicker spacer can be formed on gate structures of Logic transistors than on co-situated gate structures of non-Logic transistors. “Co-situated” means both Logic transistors and non-Logic transistors are situated on the same die. The result can be to decrease OFF state leakage in Logic transistors without closing the spacer-to-spacer gap between gate structures in stacked devices while simultaneously keeping a thinner spacer on SRAM transistors to prevent closing the spacer-to-spacer gap between gate structures in these types of arrays. Doping of the source and drain regions with respect to each class of transistors can be accomplished without blocking thereof.

It should be appreciated that the embodiments described above can apply to any combination of classes of devices depending on a designer's needs and the power/performance trade-off. That is, a first spacer of a first size can be formed on a first class of devices and a second spacer of a second size can be formed on a second class of devices wherein the classes can be different. Examples include, but are not limited to, a first class including NMOS devices and a second class including PMOS devices (or vice-versa) inside a Logic circuit; a first class including NMOS devices and a second class including PMOS devices (or vice-versa) inside a SRAM memory array circuit; a first class including both NMOS and PMOS devices inside an SRAM memory array circuit and a second class including both NMOS and PMOS devices inside a Logic circuit; or a first class including all PMOS devices inside SRAM and Logic circuits and a second class including all NMOS devices inside SRAM and Logic circuits. The combinations are virtually limitless.

FIG. 5 shows a cross-sectional side view of an integrated circuit package that is physically and electrically connected to a printed wiring board or printed circuit board (PCB) to form an electronic assembly. The electronic assembly can be part of an electronic system such as a computer (e.g., desktop, laptop, handheld, server, etc.), wireless communication device (e.g., cellular phone, cordless phone, pager, etc.), computer-related peripheral (e.g., printer, scanner, monitor, etc.), entertainment device (e.g., television, radio, stereo, tapes and compact disc player, video cassette recorder, motion picture expert group audio layer 3 player (MP3), etc.), and the like. FIG. 5 illustrates the electronic assembly as part of a desktop computer. FIG. 5 shows electronic assembly 500 including die 502, physically and electrically connected to package substrate 504. Die 502 is an integrated circuit die, such as a microprocessor die, having, for example, transistor structures interconnected or connected to power/ground or input/output signals external to the die through interconnect lines to contacts 506 on an external surface of die 502. The die may be formed in accordance with known wafer processing techniques using as the substrate described with reference to FIGS. 2A-2H. Contacts 506 of die 502 may be aligned with contacts 508 making up, for example, a die bump layer on an external surface of package substrate 504. On a surface of package substrate 504 opposite a surface including contacts 508 are land contacts 510. Connected to each of land contacts 510 are solder bumps 512 that may be used to connect package 514 to circuit board 516, such as a motherboard or other circuit board.

Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that the fabrication of a multiple metal layer structure atop a substrate, such as a silicon substrate, to manufacture silicon device is well known in the art. Therefore, it is appreciated that the figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein. 

1. A method comprising: forming a first spacer on a gate structure of a first class of transistors on a substrate wherein the first class of transistors is formed on the same substrate as a gate structure a second class of transistors different from the first class of transistors, each gate structure including a top surface opposite a surface of the substrate and opposing side surfaces, the first spacer formed on opposing side surfaces of the gate structure of the first class of transistors; forming a second spacer on the first spacer and on the gate structure of the second class of transistors; and forming a third spacer on the gate structure of the second class of transistors, selective of the gate structure of the first class of transistors.
 2. The method of claim 1, wherein forming the first spacer and the second spacer comprises: forming a first dielectric layer on the first class of transistors and the second class of transistors; selectively forming a photo-imageable layer on the second class of transistors; removing the first dielectric layer such that the first dielectric layer remains on the gate structure of the second class of transistors and a first dielectric spacer remains intact on the opposing side surfaces of the first class of transistors; removing the photo-imageable layer from the second class of transistors; forming a second dielectric layer on the first class of transistors and on the second class of transistors; removing the second dielectric layer from a top surface of the first class of transistors; and removing the remaining second dielectric layer from the second class of transistors.
 3. The method of claim 2, wherein the second dielectric layer on the second class of transistors is removed during the removing of the remaining first dielectric layer from the second class of transistors.
 4. The method of claim 2, wherein the second class of transistors are Logic transistors.
 5. The method of claim 2, wherein the first class of transistors are non-Logic transistors.
 6. The method of claim 2, wherein the first class of transistors are situated on the substrate at random.
 7. The method of claim 2, wherein the second class of transistors are one of Logic or non-Logic transistors.
 8. The method of claim 2, wherein the second class of transistors are situated on the substrate in an array or at random.
 9. The method of claim 1, wherein the substrate is a die.
 10. The method of claim 1, wherein the selectively forming comprises: forming a dielectric layer on the first class of transistors and the second class of transistors; selectively forming a photo-imageable layer on the first class of transistors wherein the dielectric layer is exposed on the second class of transistors; removing the dielectric from the top surface of the second class of transistors; and removing the photo-imageable layer from the first class of transistors.
 11. A method comprising: conformally depositing a first dielectric layer on a gate structure of a first class of transistor and on a gate structure of a second class of transistor, each gate structure having a top surface opposite a surface of the substrate and opposing side surfaces; forming first spacers from the first dielectric layer on the sidewalls of the gate structure of the first class of transistor while retaining the conformal deposition of the first dielectric layer on the gate structure of the second class of transistor; conformally depositing a second dielectric layer on the first spacers of the gate structure of the first class of transistors and the first dielectric layer on the gate structure of the second class of transistor; forming second spacers from the second dielectric layer on the first spacers of the gate structure of the first class of transistor; and removing the first dielectric layer and the second dielectric layer from the gate structure of the second class of transistor.
 12. The method of claim 11, wherein prior to forming first spacers, the method comprises: patterning a blocking layer on the gate structure of the second class of transistor.
 13. The method of claim 12, wherein following forming first spacers, the method comprises: removing the blocking layer.
 14. The method of claim 11, wherein after removing the first dielectric layer and the second dielectric layer from the gate structure of the second class of transistor, forming spacers on opposing side surfaces of the gate structure of the second class of transistor selective of the gate structure of the first class of transistor. 